The present invention relates to a semiconductor device and particularly to a pad layout in a semiconductor device (chip).
Heretofore, in a semiconductor device, die sort (selection of chips) has generally been conducted while a probe is put into contact with dice prior to separation of semiconductor integrated circuits formed on a wafer into chips. In this die sort operation, when chip sizes are same as one another, the same probe can be used in common on different dice by using the same pad layout and aligning sites of power supply pads among chips, regardless of a difference in design.
In a kind of circuit which uses a master with a predetermined pad layout like an ASIC, for example, there are a number of products which share the same chip size and same pad layout even though they employ different designs. Therefore, since the same probe can be used in common on a number of ASIC chips, the merit is great.
However, arrangement of power supply pads is different according to specifications of a product in other kinds of circuit. Accordingly, there are no pads to be specifically used for power supply which are common in all products; In the current situation, a pad which is used as a power supply pad in a product is used as a signal pad-or an NC (non-connective) pad in another product.
Therefore, generally, in addition to general purpose pads whose application can be selected for either power supply, an I/O signal or the like, pads exclusive to power supply are provided. FIG. 1 is a layout showing an example of construction and arrangement of pads in a conventional chip. As shown in FIG. 1, power supply pads 42 are arranged in the in vicinity of a corner section of a chip 40. General purpose pads 44 are arranged around the middle section of the chip 40 along the periphery thereof. When the general purpose pads 44 are I/O signal pads, the pads are respectively connected to I/O circuits 46.
In this way, the reason why power supply pads 42 are arranged in the vicinity of a corner section of the chip 40 is that when pads are located in the vicinity of a corner section, an area for forming transistors of an I/O circuit cannot be secured in an adjacent manner to each of the pads. In this case, while all power supply pads cannot take the same arrangement, at least power supply pads which are located in the vicinity of a corner section take the same arrangement. Hence, one probe for testing can commonly be used for a plurality of products.
In the construction and arrangement of pads as shown in FIG. 1, however, when connection between pads on the chip side and pins on the package side are performed by bonding with a metal wire, generally bonding is comparatively easy around the middle section of the chip along the periphery thereof, whereas bonding in the vicinity of a corner section of the chip is hard to perform. This is a problem that is caused due to a wider pitch in arrangement of pins on the package side than that of pads on the chip side.
Therefore, a method has sometimes been employed in which general purpose pads in the vicinity of a corner section of the chip are located at sites as remote from areas where transistors of the I/O circuits are formed as possible and power supply pads are not located in the vicinity of a corner section of a chip.
FIG. 2 is a layout showing such a construction and arrangement of pads. As shown in FIG. 2, in the vicinity of a corner section of the chip 50, general purpose pads 54 are arranged at a wide pitch at sites as remote from the areas where transistors of the I/O circuits 52 are formed as possible. General purpose pads 56 are arranged around the middle section of the chip 50 along the periphery thereof except the vicinity of a corner section thereof. In this case, however, a probe cannot commonly be used.